{"product_id":"system-level-test-and-validation-of-hardware-software-systems-hardcover","title":"System-Level Test and Validation of Hardware\/Software Systems - Hardcover","description":"\u003cdiv\u003e\u003cp style=\"text-align: right;\"\u003e\u003ca href=\"https:\/\/reportcopyrightinfringement.com\/\" target=\"_blank\" rel=\"nofollow\"\u003e\u003cb\u003eReport copyright infringement\u003c\/b\u003e\u003c\/a\u003e\u003c\/p\u003e\u003c\/div\u003e\u003cp\u003eby \u003cb\u003eMatteo Sonza Reorda\u003c\/b\u003e (Editor), \u003cb\u003eZebo Peng\u003c\/b\u003e (Editor), \u003cb\u003eMassimo Violante\u003c\/b\u003e (Editor)\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cp\u003eNew manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers.\u003c\/p\u003e \u003cp\u003eSOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction. Research efforts are already addressing this issue.\u003c\/p\u003e \u003cp\u003eThis monograph provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including: \u003c\/p\u003e \u003cul\u003e \u003cli\u003emodeling of bugs and defects;\u003c\/li\u003e \u003cli\u003estimulus generation for validation and test purposes (including timing errors;\u003c\/li\u003e \u003cli\u003edesign for testability.\u003c\/li\u003e\n\u003c\/ul\u003e\u003ch3\u003eBack Jacket\u003c\/h3\u003e\u003cp\u003e\u003c\/p\u003e\u003cp\u003eNew manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers.\u003c\/p\u003e \u003cp\u003eAs well as giving rise to new design practices, SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the necessary infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction such as higher functional performance and greater operating speed. Research efforts are already addressing this issue.\u003c\/p\u003e \u003cp\u003e\u003cem\u003eSystem-level Test and Validation of Hardware\/Software Systems\u003c\/em\u003e provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including: \u003c\/p\u003e \u003cp\u003e- modeling of bugs and defects;\u003c\/p\u003e \u003cp\u003e- stimulus generation for validation and test purposes (including timing errors;\u003c\/p\u003e \u003cp\u003e- design for testability.\u003c\/p\u003e \u003cp\u003eFor researchers working on system-level validation and testing, for tool vendors involved in developing hardware-software co-design tools and for graduate students working in embedded systems and SOC design and implementation, \u003cem\u003eSystem-level Test and Validation of Hardware\/Software Systems\u003c\/em\u003e will be an invaluable source of reference.\u003c\/p\u003e\u003ch3\u003eAuthor Biography\u003c\/h3\u003e\u003cp\u003e\u003c\/p\u003e\u003cp\u003eMatteo Sonza Reorda is the leader of the computer-aided design group of the Dipartimento di Automatica e Informatica, Politecnico di Torino. Zebo Peng is Professor of the chair in Computer Systems and Director of the Embedded Systems Laboratory at Linköping University.\u003c\/p\u003e\n            \u003cdiv\u003e\n\u003cstrong\u003eNumber of Pages:\u003c\/strong\u003e 179\u003c\/div\u003e\n            \u003cdiv\u003e\n\u003cstrong\u003eDimensions:\u003c\/strong\u003e 0.6 x 9.3 x 6.3 IN\u003c\/div\u003e\n            \u003cdiv\u003e\n\u003cstrong\u003eIllustrated:\u003c\/strong\u003e Yes\u003c\/div\u003e\n            \u003cdiv\u003e\n\u003cstrong\u003ePublication Date:\u003c\/strong\u003e May 03, 2005\u003c\/div\u003e\n            ","brand":"BooksCloud","offers":[{"title":"Default Title","offer_id":53376953188659,"sku":"9781852338992","price":185.18,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0300\/5595\/6612\/files\/SG5cpfUHsw9781852338992.webp?v=1779310549","url":"https:\/\/www.vysn.com\/en-ca\/products\/system-level-test-and-validation-of-hardware-software-systems-hardcover","provider":"VYSN","version":"1.0","type":"link"}